1. Field of the Invention
The present invention relates to a wiring board which comprises a plurality of device formation areas respectively for mounting semiconductor chips thereon.
2. Description of the Related Art
A MAP (Mold Array Process) technique is known as a method of manufacturing a BGA (Ball Grid Array) type semiconductor device. In the MAP technique, a BGA type semiconductor device is manufactured in the following manner. A semiconductor chip is mounted on each of a plurality of device formation areas defined on a wiring board. Next, the plurality of device formation areas which are mounted with the semiconductor chips are collectively sealed with resin. Subsequently, the wiring board is divided into the respective device formation areas to produce individual chips. Here, the wiring board is sealed with resin in the following manner. Specifically, the wiring board which is mounted with the semiconductor chips is set between an upper die and a lower die of a transfer mold device, sealing resin is filled in a cavity formed between the upper and lower dies, and the filled sealing resin is thermally cured. Consequently, the wiring board suffers from deformation (distortion) due to a thermal expansion of the wiring board resulting from heating during the molding of the sealant and due to stress produced when the wiring board is clamped between the upper and lower dies, and the like. As a result, internal stress remains in the wiring board, causing deformation of the wiring board and respective device formation areas (divided semiconductor devices) after molding. More specifically, the wiring board and semiconductor devices are warped, and variation of the warpage is large. When a semiconductor device has large warpage, the reliability of secondary mounting is degraded. Specifically, in the secondary mounting for mounting a semiconductor device on a mounting board, the favorable bump connections are not provided. Also, when a semiconductor device is mounted on another semiconductor device as in PoP (Package on Package) configuration, the semiconductor devices can fail to provide satisfactory bump connections.
JP-2000-124163A discloses technologies for forming a slit-shaped throughholes through a board along lines which partition a plurality of device mounting areas (equivalent to the above-mentioned device formation areas) before the device mounting areas which are mounted with semiconductor devices are collectively sealed with resin. According to JP-2000-124163A, the throughholes act to distribute internal stress which occurs when the board is sealed with the resin.
Further, JP-2002-76186A and JP-2003-37125A describe technologies for placing a plurality of blocks on which multiple mounting areas are formed on a strip-shaped conductive foil, and forming slits between the respective blocks. According to these publications, the slits act to absorb the stress of the conductive foil which occurs due to a heat treatment in the molding process and the like.
In the technologies disclosed in JP-2000-124163A, the slits are formed on the partitioning lines of the wiring board. However, when the wiring board is sealed with resin, regions outside of the partitioning lines are clamped by molding dies. Then, the highest temperature, and hence the largest thermal expansion is exhibited in the regions which are clamped by the molding dies. Accordingly, the technologies disclosed in JP-2000-124163A fail to sufficiently alleviate stress in the region of the wiring board which exhibits the largest thermal expansion. Further, formation of slits along the partitioning lines means that the slits are formed within the mold region on which the sealant is molded. As such, voids are highly likely to stay within the slits during the molding process. Voids remaining in the slits, if any, can cause a package to be cracked during reflow of semiconductor devices. Moreover, the sealing resin can leak to the back side of the wiring board through the slits and can cover the external terminals.
Neither JP-2002-76186A nor JP-2003-37125 definitely shows the relationship between the molding dies and conductive foil. On the other hand, JP-2002-76186A describes in Paragraph [0037], “frame pattern 66 is used for engagement with a molding die.” In view of such a description and the illustration of accompanying FIG. 4B, it is understood that slit 63 between respective blocks 62 is located outside the molding die. Accordingly, like the technologies disclosed in JP-2000-124163A, JP-2002-76186A fails to sufficiently alleviate stress the region of the wiring board which exhibits the largest thermal expansion.